Architecture of 8086 Microprocessor

Architecture of 8086 Microprocessor

The 8086 is a 16-bit microprocessor introduced by Intel in 1978. It was the first 16-bit processor in the x86 family and is widely used in embedded systems, personal computers, and industrial control systems. The architecture of the 8086 is based on the von Neumann model, which means that the instructions and data are stored in the same memory space. In this answer, we will explain the architecture of the 8086 microprocessor in detail.

Registers:

The 8086 microprocessor has 14 registers, which can be divided into three categories: general-purpose registers, segment registers, and index registers.

General-purpose registers

These registers are used to store data and perform arithmetic and logical operations. There are four general-purpose registers, namely AX, BX, CX, and DX. Each of these registers can be used as a 16-bit register or two 8-bit registers.

Segment registers

These registers are used to store the base addresses of various memory segments. The 8086 has four segment registers, namely CS, DS, SS, and ES. The CS register points to the code segment, the DS register points to the data segment, the SS register points to the stack segment, and the ES register points to the extra segment.

Index registers

These registers are used to store the offset values of various memory segments. The 8086 has two index registers, namely SI and DI. The SI register is used for source indexing, and the DI register is used for destination indexing.

Instruction Set:

The 8086 microprocessor has a rich instruction set that includes data transfer, arithmetic, logical, and control transfer instructions. The instruction set is divided into several categories, including data transfer instructions, arithmetic instructions, logical instructions, string instructions, and program control instructions.

Memory Management:

The 8086 microprocessor uses a segmented memory architecture, where the memory space is divided into several segments. Each segment has a base address, which is stored in the segment register. The offset value is stored in the index register. The effective address is calculated by adding the base address and the offset value.

Interrupts:

The 8086 microprocessor supports two types of interrupts, namely software interrupts and hardware interrupts. A software interrupt is triggered by an instruction in the program, whereas a hardware interrupt is triggered by an external device such as a keyboard or a timer. When an interrupt occurs, the microprocessor saves the current state of the program and jumps to the interrupt service routine (ISR) to handle the interrupt.

Bus Interface Unit (BIU):

The BIU is responsible for fetching instructions and data from memory and transferring them to the execution unit. It also manages the segment registers and the instruction pointer (IP) register.

Execution Unit (EU):

The EU is responsible for executing instructions and performing arithmetic and logical operations. It contains the ALU, the flags register, and the control unit.

Timing and Control:

The timing and control signals are generated by the control unit. The control unit generates the signals required for instruction fetching, execution, and memory access. It also generates the signals required for interrupt handling and I/O operations.

Addressing Modes:

The 8086 microprocessor supports several addressing modes, which determine how the effective address of an operand is calculated. The addressing modes include register addressing, immediate addressing, direct addressing, indirect addressing, indexed addressing, and based addressing.

Register addressing

The operand is stored in a register.

Immediate addressing

The operand is a constant value that is included in the instruction itself.

Direct addressing

The operand is stored in a memory location whose address is specified in the instruction.

Indirect addressing

The operand is stored in a memory location whose address is stored in a register.

Indexed addressing

The effective address is calculated by adding the base address in a segment register and the offset value in an index register.

Based addressing

The effective address is calculated by adding the base address in a segment register, the offset value in an index register, and a constant displacement value.

Memory Segmentation:

The 8086 microprocessor uses a memory segmentation scheme that allows it to access up to 1 MB of memory. The memory space is divided into several segments, each of which has a maximum size of 64 KB. The segment registers hold the base address of each segment, and the instruction pointer (IP) holds the offset within the segment.

Operating Modes:

The 8086 microprocessor supports two operating modes, namely the real mode and the protected mode. In real mode, the microprocessor can access up to 1 MB of memory and runs in a single-tasking environment. In protected mode, the microprocessor can access up to 16 MB of memory and supports multiple tasks and memory protection.

Pin Configuration:

The 8086 microprocessor has a 40-pin dual in-line package (DIP) that includes several power and ground pins, address and data bus pins, control and status pins, and clock and reset pins.

I/O Interface:

The 8086 microprocessor has a built-in I/O interface that supports input/output operations. The I/O interface includes the I/O address bus, the I/O data bus, and control signals for I/O operations.

Interrupts:

The 8086 microprocessor supports interrupts, which are signals that are used to interrupt the normal program flow and transfer control to a specific interrupt service routine (ISR). The 8086 microprocessor has 256 interrupt vectors, each of which points to an ISR in memory.

Instruction Set:

The 8086 microprocessor has a rich instruction set that includes data transfer, arithmetic and logic operations, branching, and I/O instructions. The instruction set is classified into several groups, including data transfer instructions, arithmetic instructions, logic instructions, program control instructions, and I/O instructions.

Timing and Control:

The 8086 microprocessor uses a crystal oscillator to generate a clock signal that synchronizes its operations. The microprocessor has several control signals, including the interrupt request (INT), non-maskable interrupt (NMI), ready (RDY), hold (HLDA), and reset (RESET) signals.

Bus Interface:

The 8086 microprocessor uses a tri-state bus interface that includes an address bus, a data bus, and control signals. The address bus is 20 bits wide and supports up to 1 MB of memory. The data bus is 16 bits wide and supports bi-directional data transfer. The control signals include read (RD), write (WR), and several status signals.

Coprocessor Interface:

The 8086 microprocessor has a built-in coprocessor interface that allows it to communicate with an optional math coprocessor. The coprocessor interface includes a separate data bus, control signals, and several status signals.

Instruction Queue:

The 8086 microprocessor has a 6-byte instruction queue that stores up to six instructions that have been prefetched from memory. The instruction queue improves performance by allowing the microprocessor to execute instructions in parallel.

Debugging and Testing:

The 8086 microprocessor has several debugging and testing features, including the single-step mode, the trace mode, and the hardware breakpoint feature. These features allow the programmer to monitor the execution of the program and debug any errors that may occur.

In conclusion, the architecture of the 8086 microprocessor is based on the von Neumann model and includes 14 registers, a rich instruction set, segmented memory management, interrupt handling, a BIU, an EU, and timing and control signals. The architecture of the 8086 microprocessor has been widely used as a basis for many modern microprocessors and is still used in many embedded systems and industrial control systems today.